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conftrace_

hardware description language

5 papers

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Also known as

HDL

Co-occurring keywords · papers mentioning both

code generation (4) hardware vulnerability detection (1) traversal detection pattern (1) rtl synthesis (1) property graph (1) large language model (1) two-stage training (1) neuro-symbolic reasoning (1) abstract syntax tree (1) intermediate representation (1)

Papers

QiMeng-CRUX: Narrowing the Gap Between Natural Language and Verilog via Core Refined Understanding eXpression AAAI 2026 SYMDIREC: A Neuro-Symbolic Divide-Retrieve-Conquer Framework for Enhanced RTL Synthesis and Summarization EACL 2026 VerilogLAVD: LLM-Aided Pattern Generation for Verilog CWE Detection ACL 2026 CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair ICLR 2025 VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool AAAI 2025