conftrace_

hardware design

11 papers

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Co-occurring keywords · papers mentioning both

high-level synthesis (2) graph neural network (2) chip placement (2) field programmable gate array (2) transfer learning (2) reinforcement learning (2) deep reinforcement learning (2) wirelength reduction (1) 3d integrated circuit (1) rtl code generation (1)

Papers

PrefixGPT: Prefix Adder Optimization by a Generative Pre-trained Transformer AAAI 2026 DeepRTL2: A Versatile Model for RTL-Related Tasks ACL 2025 Hierarchical Mixture of Experts: Generalizable Learning for High-Level Synthesis AAAI 2025 The Graph’s Apprentice: Teaching an LLM Low-Level Knowledge for Circuit Quality Estimation IJCAI 2025 BBQ: A Fast and Scalable Integer Priority Queue for Hardware Packet Scheduling NSDI 2024 FlexPlanner: Flexible 3D Floorplanning via Deep Reinforcement Learning in Hybrid Action Space with Multi-Modality Representation NeurIPS 2024 Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs NeurIPS 2024 ChiPFormer: Transferable Chip Placement via Offline Decision Transformer ICML 2023 DevFormer: A Symmetric Transformer for Context-Aware Device Placement ICML 2023 Towards a Comprehensive Benchmark for High-Level Synthesis Targeted to FPGAs NeurIPS 2023 MaskPlace: Fast Chip Placement via Reinforced Visual Representation Learning NeurIPS 2022