Skip to content
conftrace_
2024 NeurIPS NeurIPS 2024

Fast Channel Simulation via Error-Correcting Codes

We consider the design of practically-implementable schemes for the task of channel simulation. Existing methods do not scale with the number of simultaneous uses of the channel and are therefore unable to harness the amortization gains associated with simulating many uses of the channel at once. We show how techniques from the theory of error-correcting codes can be applied to achieve scalability and hence improved performance. As an exemplar, we focus on how polar codes can be used to efficiently simulate i.i.d. copies of a class of binary-output channels.

More from NeurIPS 2024

All NeurIPS 2024 papers →