conftrace_

chip design

8 papers

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Co-occurring keywords · papers mentioning both

reinforcement learning (4) macro placement (3) electronic design automation (3) collaboration system (1) generative routing (1) mixed-size macro placement (1) global routing (1) overflow avoidance (1) network distillation (1) placement and routing (1)

Papers

RSPlace: Rotation Sensing Macro Placement via Bidirectional Tree Expansion AAAI 2026 Divergent Thoughts toward One Goal: LLM-based Multi-Agent Collaboration System for Electronic Design Automation NAACL 2025 LaMPlace: Learning to Optimize Cross-Stage Metrics in Macro Placement ICLR 2025 CircuitNet 2.0: An Advanced Dataset for Promoting Machine Learning Innovations in Realistic Chip Design Environment ICLR 2024 NeuralSteiner: Learning Steiner Tree for Overflow-avoiding Global Routing in Chip Design NeurIPS 2024 Reinforcement Learning Policy as Macro Regulator Rather than Macro Placer NeurIPS 2024 The Policy-gradient Placement and Generative Routing Neural Networks for Chip Design NeurIPS 2022 On Joint Learning for Solving Placement and Routing in Chip Design NeurIPS 2021