electronic design automation

CODMAS: A Dialectic Multi-Agent Collaborative Framework for Structured RTL Optimization EACL 2026 KCLNet: Electrically Equivalence-Oriented Graph Representation Learning for Analog Circuits AAAI 2026 Bridging Layout and RTL: Knowledge Distillation based Timing Prediction ICML 2025 DeepRTL2: A Versatile Model for RTL-Related Tasks ACL 2025 Divergent Thoughts toward One Goal: LLM-based Multi-Agent Collaboration System for Electronic Design Automation NAACL 2025 Automated CPU Design by Learning from Input-Output Examples IJCAI 2024 BetterV: Controlled Verilog Generation with Discriminative Guidance ICML 2024 CircuitNet 2.0: An Advanced Dataset for Promoting Machine Learning Innovations in Realistic Chip Design Environment ICLR 2024 Reinforcement Learning Policy as Macro Regulator Rather than Macro Placer NeurIPS 2024 Towards Automated RISC-V Microarchitecture Design with Reinforcement Learning AAAI 2024 Circuit as Set of Points NeurIPS 2023 CktGNN: Circuit Graph Neural Network for Electronic Design Automation ICLR 2023 Macro Placement by Wire-Mask-Guided Black-Box Optimization NeurIPS 2023 Versatile Multi-stage Graph Neural Network for Circuit Representation NeurIPS 2022